Product description

The VPE consists of a reaction chamber and a lid. A heating element is integrated in the lid. It controls the temperature of the substrate to be etched. Wafer clamping can be achieved in two ways: Wafers can be clamped mechanically by using the clamping ring. The screwing is done from the backside of the apparatus, which is never in contact with the HF vapor. The 3 nuts are easy to handle with protection gloves. The other option is electrostatic clamping. Single chips (longer than 10 mm) as well as wafers can be clamped to the heating element. The backside of the wafer is protected from etching.

Sticking of MEMS

Silicon dioxide is often used as a sacrificial layer for micromachined structures. For example, Deep Reactive Ion Etched (DRIE) devices on Silicon on Insulator (SOI) wafers are often released in liquid Hydrofluoric acid (HF).
After rinsing the wafer in DI water the surface tension of water destroys the liberated structures or the structures stick to each other.

Solution

Etching silicon dioxide in HF vapor is a quasi dry process. Due to the humidity in the HF vapor atmosphere a very thin water film is present on the wafer. HF is absorbed and etches the silicon dioxide (SiO2). During the reaction, Silane and water is produced. The Silane escapes in the gas phase. It is interesting to see that in this reaction water acts as an initiator and is produced by the process itself. In heating the substrate, the etch rate can be adjusted by controlling the amount of water on the surface. At etch rates of 4-6 um/hrs most structures can be released without sticking. The etching progress and homogenity are shown in the following pictures. Before test: Silicon wafer with 1 um thermal oxide After 25min: Typical rings appear. The large inner part of the same color indicates a homogenous etching After 30min: Some oxide is left After 35min: All oxide is removed on 80 % of the wafer diameter.

The etching progress and homogenity are shown in the following pictures.

Before test: Silicon wafer with 1 um thermal oxide	After 25min: Typical rings appear. The large inner part of the same color indicates a homogenous etching
After 30min: Some oxide is left	After 35min: All oxide is removed on 80 % of the wafer diameter

Application

Summary

- Sticking free MEMS release
- Structure thinning
- Dicing free release of structures on SOI substrates
- Etch-rate adjustable from 0 to about 30 µm/h
- Single side SiO2 etching (back-side protected during process)

Release of Comb Drive Structure

Sticking free release of Comb drives with 1 µm gap between adjacent comb fingers (Picture source: Idonus Sarl)

	Dicing free Release of Optical MEMS Intelligent double sided deep reactive ion etching enables dicing free release of chips on wafer level (Picture source: IMT University of Neuchatel)
	Structure Thinning Consecutive oxidation and HF VPE enables the fabrication of sub-micron diameter torsion beams (Picture source: IMT University of Neuchatel)
	Photonic Bandgap Nanometric membranes on thin sacrificial layers can easily be released (Picture source: IMT University of Neuchatel)
	Isle Structures Timed etching allows the fabrication of isle structures (bright) that are only suspended by the remaining SiO2. The darker structures are released. (Picture source: IMT University of Neuchatel)
	Thin Film Applications 0.5 µm thick Poly-silicon beams released on 1 µm thermal SiO2: The width of the beams is 10 µm, the length varies from 100 to 500 µm (Picture source: Idonus Sarl)
	Etch Rates of small Openings The holes were dry-etched into 0,5 µm of poly-silicon deposited on 1 µm of thermal SiO2. The etch rate of the sacrificial SiO2 depends on the diameter of the opening. Neither sticking nor "bad wetting" (liquids that do not diffuse into small holes) of the small openings occurred. (Picture source: Idonus Sarl)
	Aluminum Structures Aluminum structures on SiO2 can be released. The high stress in the aluminum cantilevers causes a strong curling. The 0,5 µm thick aluminum layer was deposited on 1 µm thermal SiO2. (Picture source: Idonus Sarl)

Technology: vapor phase etching

First experiments on vapor phase etching were carried out by Holmes & Snell in 1966 [1]. They observed that silicon dioxide on a wafer is etched with a comparable etch rate even when the wafer is not in the etch bath but close to. Helms & Deal established that the role of water is to provide a condensed solvent medium for the HF on the surface. Offenberg et al. [2] proposed a two step reaction where first the oxide surface is opened by formation of silanol groups by adsorbed water (H2O ) . Subsequently silanol groups are attacked by the HF:

SiO₂ + 2H₂O -> Si(OH)₄

Si(OH)₄ + 4HF -> SiF₄ + 4H₂O

The above formula shows that water acts as initiator of the etching process as well as reactant. This fact suggests that the etching process can be temperature controlled in order to maintain in equilibrium the amount of water needed to initiate the process and the amount of reactant water . In idonus' Vapor Phase Etcher this equilibrium is achieved by heating the wafer. The water film on the wafer is evaporated at moderate temperatures. The etch rate decreases with increasing temperature and stops completely at temperatures above 50°C.
Sticking free MEMS release is achieved at etch rates around 5 µm/h.

For further information ask our skilled team for assistance!


[1] P. J. Holmes and J. E. Snell, Microelectronics and Reliability (Pergamon, New York 1966), Vol. 5, p. 337.

[2] M. Offenberg, B. Elsner, and F. Lärmer, "Vapour HF etching for sacrificial oxide removal in surface micromachining", Extended Abstracts: Electrochem. Soc. Fall Meeting (Miami Beach) vol 94-2, pp 1056-7, 1994.

Publications

COMBINED AL-PROTECTION AND HF-VAPOR RELEASE PROCESS FOR ULTRATHIN SINGLE CRYSTAL SILICON CANTILEVERS
S. Mouaziz; Microsystems Laboratory, Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland

ETCH STOP MATERIALS FOR RELEASE BY VAPOR HF ETCHING
Thor Bakke; Fraunhofer IPMS, Dresden, Germany
16th MME Workshop 2005, Goeteborg, Sweden

QUASI-DRY RELEASE FOR MICRO ELECTRO-MECHANICAL SYSTEMS
M. Zickar; SAMLAB, Institute of Microtechnology (IMT), University of Neuchatel, Switzerland

A CLEAN WAFER-SCALE CHIP-RELEASE PROCESS WITHOUT DICING BASED ON VAPOR PHASE ETCHING
T. Overstolz; SAMLAB, Institute of Microtechnology (IMT), University of Neuchatel, Switzerland

Reaction chamber temperature control

The etch rate of silicon dioxide varies slightly with the temperature of the liquid HF in the reaction chamber. The temperature of the HF depends on the ambient temperature of the clean room. Additionally, the HF heats during long etching processes, which results in an increasing etch rate from wafer to wafer until the system has stabilized. To stabilize the etch rate we have developed a reaction chamber with temperature controlled HF in the container. The temperature of the HF can be adjusted with an additional controller. A Peltier element heats or cools the acid depending on the desired process parameters.

HF vapor phase release service for MEMS

We offer a release service for MEMS wafers as well as single chips.
All the manipulations are carried out in a clean room. As every application is different we are pleased to discuss the release of your MEMS with you.